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Digital Signal Processing, DSP
1. Introduction

Embedded Systems overview
Example Embedded Systems and their Requirements
Design Challenges, Metrics
Processor technologies
IC technology
Programmable Logic Devices
FPGA Programming Mode

2. VHDL Introduction

VHDL Entities and architectures
Standard Logic Vectors
Signals, In, Out, Inout
Execution Order, RTL
Structural, Dataflow, Behavioral

3. Hardware background: Combinational Logic

Wires, Drivers, Transistors, logic gates
Combinational Logic, Multiplexors, Decoders, Encoders

4. VHDL Cont

A First VHDL Design: XOR3
ModelSim, Do Files
Decoders, Encoders
Generics, Int type, Generates
Synthesizable, behavioral VHDL constructs

5. FPGA Structure

FPGA architecture
Configurable Logic Block Structure (CLB), wiring
On chip wiring: Global routing matrix,
global, long, hex and single lines
Memory hierarchy: LUTs, Block RAM, external memory
IO blocks


The SPARTAN FPGA processor
Block RAM
Oscilator, clocks,
Buttons, switches,
LEDs, Seven segment displays, VGA
Serial ports, parallel ports, keyboard and mouse ports

7. FPGA Design Flow

Design Entry
Place and Route

8. Sequential VHDL

Flip-flops, Registers
Sequential processes
dff.vhd, dreg.vhd, shift_register.vhd, shift_register2.vhd, counter.vhd.
Finite State Machines
State types, next/current values, Encoding Schemes
Pulse generators and events
Driving a block of 7 segment displays, ROM tables
Complex state machines and combinational processes
SVGA Controller

9. EDK Structure

A soft processor in VHDL:
The Xilinx EDK
Block RAMs
Busses, OPB/LMB
Peripherals, UART, GPIO

10. EDK Programming

Software debugging, GDB, MDM
UART, GPIO, detecting button presses
Event handlers, timers, FSLs
Building an SVGA system in the Spartan
Using BlockRAMs in the SVGA system

11. A System on a Chip

Connect four, alpha-beta search
EDK Architecture
Board evaluation in software
Board evaluation in hardware
The Trainers
Mr. Hong, professor
The Acchievement

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RF Glossary and Terms

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